19.2: 5GHz CMOS Radio Transceiver Front-End Chipset

Incorporating the direct conversion architecture, a 5GHz band radio transceiver front-end chipset for wireless LAN applications is implemented in a 0.25-microns CMOS technology. The 4 mm sup 2 5.25GHz receiver IC contains an LNA with 2.5 dB NF and 16 dB power gain, a receiver mixer with 11.95 dB SSB NF and 13.7 dB voltage gain. The 2.7 mm sup 2 transmitter IC achieves an aouput 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4 dB (image) sideband rejection by using an integrated quadrature VCO. Operating from a 3V supply, the power consumptions for the receiver and transmitter are 114 mW and 120 mW, respectively.