2K Gate Circuits With 100 ps Gate Delay Using GaAs HFET Technology

Four digital circuits were processed with the Self-Aligned Refractory Gate process, in the DARPA III GaAs Pilot Line. Heterojunction E/D FET technology, with 1micron channel length and a single power supply of 2V, was used to implement a 32-bit ALU, dual 8x8 parallel multiplier, quad 4-bit adder, and a SRAM tester.