2K Gate Circuits with 125 ps Gate Delay Using GaAs HFET Technology

Four digital circuits were processed with the Self-Aligned Refractory Gate process, in the DARPA III GaAs Pilot Line. The GaAs/AlGaAs heterostrucure E/D FET technology (HFET) with 1um channel length and a nominal power supply of 2V was used to implement a 32-bit ALU, a dual 8x8 parallel multiplier, a quad 4-bit adder, and a SRAM tester. The measured propagation delay per gate is 125 ps for the ALU, and 132 ps for the multiplier.