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    A 0.6micron CMOS Technology for High Performance Application - Twin-Tub VI

A 0.6micron CMOS Technology for High Performance Application - Twin-Tub VI

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This paper reports on the process/structure integration of a 0.6micron 3.3V twin-tub CMOS technology with N sup + /P sup + gate, salicide shallow junctions, fully planarized D1, tungsten plug window, and two level metal structure. The n-channel and p-channel devices are closely symmetric in vertical dimensions, channel lengths, and threshold voltages.