A 0.75micron Minimum Linewidth Two-Level Metal Process Using Plasma CVD TEOS Interlevel Dielectric

Topography related issues increasingly dominate the process design of micron and submicron VLSI interconnect technologies. Depth of focus limitations for fine line patterning, line width control over rough topography, sputter deposition step coverage, as well as etch residues along steep edges are highlighting the need for surface smoothing.