A 10 GHz frequency divider using Selectively Doped Heterostructure Transistors.

We report the first complementary clocked frequency divider using dual gate Selectively Doped Heterostructure Transistors (SDHT). The circuit employs a master-slave flip-flop design which consists of four direct coupled AND-NOR gates. The nominal gate length and the gate-gate spacing are 1micron. A maximum dividing frequency of 10.1 GHz at 77 K was achieved, at this frequency the circuit dissipated 49.9 mW at 1.67 V bias. This is the highest operating frequency reported for static frequency divders at any temperature. At room temperature the dividers were operated successfully at frequencies up to 5.5 GHz with a total power dissipation of 34.8 mW at 1.97 V bias. The lowest speed-power product at room temperature was obtained at 5 GHz with 14.9 mW power dissipation at 1.45 V bias.