A 100 MHz 40-Tap Programmable FIR Filter Chip

This paper describes the design and implementation of a single chip programmable 40-tap FIR filter in 0.9mu CMOS technology. The chip has been fabricated and tested at sample rates up to 100 MHz. It performs over 4 billion multiply-add operations (12 x 10 bit multiplications and 26-bit additions) per second in less than 22 mm sup 2 of silicon area while dissipating about 3.1 Watts of power.