A 1.0micron CMOS two-level metal technology incorporating plasma enhanced TEOS.

One of the most challenging technology issues in multilevel metallization is the choice of an appropriate intermetal dielectric material and its associated processing. In this paper the two level metal process for a fourth generation twin-tub CMOS technology is presented. This technology relies on the use of an interlevel dielectric deposited in an in-house reactor by plasma enhanced CVD of tetraethylorthosilicate (PETEOS). Because the step coverage of this film is far superior to that of silane based oxides, complicated processing sequences are not required in order to smooth underlying topography. The interlevel dielectric scheme consists of a thick deposition of PETEOS followed by an anisotropic reactive ion etch. With this approach, closely spaced lines in first level metal are completely planarized with no void formation while the topography at isolated features is smoothed by the radius of curvature of the thick deposition. This simple processing sequence is extremely important in a manufacturing environment.