A 112-GS/s 1-to-4 ADC front-end with more than 36-dBc SFDR and 28-dB SNDR up to 43-GHz in 130-nm SiGe BiCMOS

Voltage-mode sampling circuits operating at mm-wave frequen-cies require clocks with root-mean-squared (RMS) jitter in the two-digit femtosecond range for high SNR performance. The generation of such clean clocks, however, presents a serious de-sign challenge. To mitigate this problem, an alternative sampling approach based on charge sampling is proposed. For the same RMS clock sampling jitter, this approach can enable SNR im-provements of up to 3 dB over voltage-mode sampling. The pro-posed concept is used for the implementation of a 112 GS/s 1-to-4 ADC front-end in IHP 130 nm SiGe BiCMOS. In experimental tests, the ADC front-end achieves more than 36 dBc SFDR and more than 28 dB SNDR up to 43 GHz. Furthermore, 100 GS/s data sampling of 80 Gbaud PAM-4 signals with an EMV of 10% for 40k received symbols is presented.