A 12-b, 650-MSps time-interleaved pipeline analog to digital converter with 1.5 GHz analog bandwidth for digital beam-forming systems

This paper presents the design of a very low power 12-bit 650-MSps time-interleaved pipeline analog-to-digital converter (ADC) for digital beam forming applications. A novel mixed-signal calibration technique is used to compensate for sample-time error between interleaved channels. A front-end sample-and-hold amplifier (SHA) is also designed as an alternative to demonstrate the effectiveness of the proposed technique. The ADC is designed in IBM BiCMOS 8HP 0.13 um. With the SHA the total power consumption of the ADC is 422 mW and SNDR of 65 dB is achieved up to 61 MHz of signal bandwidth. Using the proposed calibration scheme, there would be no need for SHA and the ADC power consumption is reduced to 335 mW in the normal operation of the ADC while SNDR is increased to 70.8 dB with the same input frequency. Simulation results also show that the proposed technique is able to improve the SNDR of a 12-bit time-interleaved ADC by 29 dB at 37 % of the Nyquist rate frequency.