A 1.25 GS/s 7 b SAR ADC With 36.4 dB SNDR @ 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28 nm CMOS

This paper presents a 1.25 GS/s 7 b single-channel Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist are 40.1/52 dB and remain still 36.4/50.1 dB at a 5 GHz input frequency (8th Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34 dB SNDR single-channel SAR ADCs, is accomplished by a Triple-Tail dynamic comparator and a Unit-Switch-Plus-Cap (USPC) capacitive DAC (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28nm bulk CMOS occupies a core area of 0.0071mm2 and consumes 3.56mW from a 1V supply, leading to a Walden Figure-of-Merit of 34.4 fJ/conversion-step at Nyquist.