A 12b 1MHz Capacitor Error Averaging Pipelined A/D Converter

This paper describes a capacitor error-averaging technique to implement a high- resolution pipelined ADC, which exhibits a 12 bit linearity at a 1 MHz sampling rate. Using a 1.75microns CMOS technology, the prototype chip occupies 14mm sup 2 and dissipates 400mW with a 5V single supply.