A 14-b 150MS/s CMOS DAC with a Background Calibration

The current-steering digital-to-analog converter (DAC) is getting more popular in high-speed communication applications for its simple architecture and potentially high-speed operation. However, the performance of the current-steering DAC is limited by its inherent mismatch of devices. By taking advantage of statistical averaging, layout techniques and random switching order, accuracy of up to 14 bits has been reported [1]. However, this technique comes with large chip size which introduces large parasitic interconnect capacitance that severely degrade the overall DAC speed. To achieve even higher accuracy or to increase yields with less layout area, calibration techniques are often used as in [2]. While the self-calibrated DAC has less parasitic effects, and is less sensitive to aging, temperature, and process variation, this technique has three inherent drawbacks [2-4]: inaccuracy due to channel-charge injection and leakage current, limited compensation range only for I DAC