A 2-1600 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction

The clock-recovery PLL requires >50% VCO tuning range to accommodate CMOS process variations. In a macro-cell PLL used in applications at different frequencies, the tuning range must be even larger. This requires special techniques for initial locking, since no phase detector for NRZ data operates reliability with a large initial frequency offset. A modification of the circuit results in a PLL that first generates a number of clock phases and than selects one of these phases as the recovered clock. In most communication systems, the data rate is specified to within a few hundred ppm, so an appropriate choice of fref and N makes the generated clocks have a frequency close to the data rate, avoiding initialization/start-up procedures