A 3.25Gb/s Injection Locked CMOS Clock Recovery Cell

A clock signal embedded in a NRZ (Non Return to Zero) 2 sup (31) -1 pseudo-random data stream is used to injection lock a slave CMOS LC tank circuit. The slave oscillator in turn generates a clock signal responsive to this stimulus and is used to capture the data. A measured Bit Error Rate (BER) of less than 2E-15 at 3Gb/s is achieved using conventional 0.25 micron CMOS and dissipating less than 50mW. Differential clock recovery can be performed with as little as four active devices.