A 3V Low-Power 0.25microns CMOS 100Mb/s Receiver for Fast Ethernet

A 125Mbaud receiver for 10/100 fast ethernet has been implemented in a 3V 0.25microns digital CMOS process. Detailed testing show excellent receiver results with error free performance up to 140m. The analog receiver including an automatic gain control (AGC) circuit with baseline wander correction, an equalizer and a DC offset correction is tuned by a digital adaptation circuitry. The analog receiver consumes 25mA from a single 3.3V power supply.