A 400 MHz CMOS Packet Transmitter-Receiver Chip

The high performance CMOS transmitter-receiver chip consists of two functionally independent sections which can simultaneously transmitter section receives byte-wide datum at 40MB/s and transforms them into 10 bit words through an on-chip encoder. The encoded words pass through a high speed parallel to serial converter and form a single bit serial output of 400Mb/s. The receiver section performs the reversed operations. It receives a 400Mb/s serial data and converts it into 10 bit words using a high speed serial to parallel converter. The received words are used to recover the original byte-wide datum through an on-chip decoder. The encoding scheme is designed to maintain a high transition density in the serial bit stream for efficient clock recovery and proper AC coupled high speed input and output.