A 400-ms/s frequency translating bandpass sigma-delta modulator

A bandpass Sigma-Delta modulator is described in this paper that uses frequency translation inside the Sigma-Delta modulator loop to take advantage of the attributes of both continuous-time and discrete-time circuits. A CMOS direct-conversion modulator digitizes a 200-kHz intermediate-frequency signal centered at 100 MHz and produces baseband I/Q outputs with a peak signal-to-noise ratio of 54 dB, Images due to I/Q mismatches are suppressed by 50 dB, This 0.35-mu m digital CMOS chip operates from a 2.7/3.3-V supply, dissipates 330 mW, and occupies 3.2 mm(2).