A 45 MHz CMOS Phase/Frequency-Lock Loop for Timing Recovery
A monolithic 45 MHz CMOS phase/frequency-locked loop circuit for timing recovery that can capture and lock over a +/-30% initial frequency offset range has been developed. This IC provides all the functions necessary to capture and recover the clock as well as re-time the data from a 45 Mbit/s pseudorandom non-return-to-zero data stream. This circuit, implemented in a 1.7Mu CMOS process, occupies 3 mm sup 2 of silicon area and consumes 250mW from a 5V supply.