A 50ns 16X16 bit 2's Complement Parallel Multiplier

This paper presents a 16x16 bit parallel multiplier in two level metal 1.0um twin tub CMOS technology. The multiplier, implemented using a customized standard cell approach, has a worst case multiplication time of 50ns in one clock cycle, dissipates less than 100mW and occupies an area of 1.2mm x 2.5mm.