A 5.3 GHz Programmable Divider for HiPerLAN in 0.25 micron CMOS

A 5.3 GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D flip-flop, (DFF). An improved glitch-free phase switching technique through the use of a retimer circuit is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25 micron CMOS technology occupies 0.09 mm sup 2 and consumes 24 mA at 1.8V and 37 mA at 2.5V. 5. 5 GHz operation with 300m V sub (pk) single-ended input is achieved with a 2.2V supply. The residual phase noise at the output is -130 dBc/Hz at an offset of 1 kHz from the carrier.