A 5GS/s 12b 158.6mW Passive-Sampling 8x-Interleaved Hybrid ADC With 9.4 ENOB and 160.5dB FoM in 28nm CMOS

Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined or pipelined-SAR architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a front-end buffer. This buffer often dissipates more power than the ADC itself. Moreover, it significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used. This work aims to maximize the input BW and dynamic performance, while inimizing the power of GHz-range high-resolution ADCs, with a 5GS/s passive-sampling, fully-dynamic, 3-stage pipelined-SAR hybrid. Removing the front-end buffer offers at least 2x power reduction, while an input BW larger than 6GHz and a Nyquist performance of 9.4ENOB and 160.5dB FoMS are enabled by the combination of: (1) very low resistance/capacitance passive input network and proper on-chip termination; (2) on-chip clock division and distribution with negligible jitter; and (3) optimized design of each sub-ADC to deliver maximum speed´resolution/power. On top, combined sub-ADC/TI analog/digital calibration is employed to assist performance.