A 60ns CMOS DSP with On-Chip Instruction Cache

This paper describes a programmable 16-bit fixed point Digital Signal Processor (DSP) instruction cycle time of 60 ns. The 51 sqmm chip was processed using an advanced 1.0 um, twin-tub, double level metal, CMOS technology (Figure 1). The processor is an enhanced Harvard architecture incorporating an on-chip instruction cache memory for efficient vector operations. An improved full custom design methodology was employed to design and verify the circuit design and layout.