A 70 MHz 8 bit x 8 bit parallel pipelined multiplier in 2.5 micron CMOS.

In this paper we present a design for an 8 bit x 8 bit parallel pipeline multiplier for high-speed digital signal processing applications. The multiplier is pipelined at the bit level. The first version of this multiplier has been fabricated in 2.5 micron CMOS technology. It has been tested at multiplication rates up to 70 MHz with a power dissipation of less than 250 mW. Such performance levels have not been reported before for any multiplier, pipelined or non-pipelined, in silicon technology. Clock skew is a major problem encountered in every highspeed pipeline architecture. This problem is overcome by the use of a balanced clock distribution network all on metal, and proper use of clock buffers. These issues and the timing simulation of the pipeline design are discussed in detail. Extensions and improvements of this work, aimed at achieving higher performance levels, will be described.