A 84 Gb/s SiGe BiCMOS duobinary serial data link including SERDES and 5 tap FFE
19 February 2015
"This paper demonstrates a serial 84 Gb/s electrical duobinary link consuming 2 W from a 2.5 V supply for Tx and Rx including a 4:1 MUX and a 1:4 DEMUX. The circuits are designed in 130 nm SiGe BiCMOS and occupy 7.1 mm2 and 5.0 mm2 for Tx and Rx respectively. The Tx includes a 4:1 MUX followed by a 5-tap FFE featuring full speed test ports. The Rx consists of a duobinary front end with two parallel multistage levelshifting limiting amplifiers connected to the 1:4 DEMUX. A BER of -11 is achieved over a channel with 14 dB loss at Nyquist."
