A Bit-Slice Architecture for Sigma-Delta Analog to Digital Converters

The Sigma Delta analog to digital converters are based on the filtering and undersampling by the digital section of the one-bit output stream coming from the modulator. The structure of this section, consisting of a sinc cubic FIR filter decimator followed by an IIR decimator section, is discussed. It is shown that both from signal processing, as well as, hardware implementation is advantageous to have the decimation factor of the first stage as large as possible. A bit-slice implementation of the decimation stages is given. It has the advantage that it can be easily expanded when higher bit resolutions are required. An application for a dual codec using only one power supply, implemented in 1.5u CMOS technology is given.