A Brownian Flow Model for a Cell-Relay Switch with Shared Buffers and Loss Priorities

This paper models the performance of a cell-relay architecture that shares buffer space among output trunks. Such an architecture has been proposed by several authors to use memory efficiently on the customized hardware required to support gigabit-per-second rates. One way to support multiple grades of service on this architecture is to divide the shared buffer into multiple priority regions delimited by successively higher thresholds. When the content of the shared buffer exceeds the p sup (th) threshold, the cell-relay switch discards arriving cells with priority less than p + 1. For such a switch with loss priorities based either on the identity of sources or on the state of a bit in the cell header, our model estimates cell-loss probabilities per priority class.