A Closer 'look' at Modern Gate Oxides

As the thickness of the gate oxide in high performance CMOS devices drops below 3 nm, local thinning on the atomic scale can have detrimental consequences on the reliability of the dielectric. In addition, interfacial roughness at the substrate side and at the poly side of the dielectric constitute an increasing part of the total oxide layer. Using high resolution TEM, we investigated different kinds of process induced 'weak spots' in SiO sub 2 layers: First, we observed thinning in the periphery of the transistor, i.e., near the boundary to the shallow trench isolation. At the boundary to the shallow trench, the Si substrate gradually changes its orientation from to , which results in an unexpected oxidation behavior in this region. Secondly, we observe the intrusion of poly-Si grains from the gate into the gate oxide, resulting in local thinning of the dielectric. Electrical data suggest that these effects are responsible for higher leakage currents and lower reliability of high performance transistors.