A Closer 'Look' at Modern Gate Oxides

Using high resolution TEM (HRTEM), we identified some process induced "weak spots" in SiO sub 2 layers. First, we observed thinning in the periphery of the transistor, i.e., near the boundary to the shallow trench isolation. At the boundary to the shallow trench, the Si substrate gradually changes its orientation from to , which results in an unexpected oxidation behavior in this region. Secondly, we observed the intrusion of poly-Si grains from the gate into the gate oxide, resulting in local thinning of the dielectric. Using image simulations, we show that conventional high resolution TEM can reveal the interface roughness only to a very limited extent.