A CMOS Mixed-Signal 100Mb/s Receive Architecture for Fast Ethernet

A 125Mbaud quad transceiver for 10/100 fast ethernet has been designed in a 5V 0.35micron digital CMOS process. Power consumption for the device is 3W. Detailed testing show excellent receiver results with error free performance up to 160m under worst-case baseline wander and crosstalk conditions. The analog receiver uses digital adaptation circuitry to optimize an automatic gain control circuit with baseline wander correction, an equalizer and a DC offset correction circuit.