A CODEC with On-Chip Digital Echo Canceller

A 1.5mu CMOS technology codec, using SIGMA-DELTA conversion techniques, which incorporates the hybrid echo cancellation on-chip is described. The echo cancellation is done in two stages; an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter. The limiting effects of the variation of the analog components on the echo cancellation performance of the device are minimized, such that only one set of coefficients per national standard is necessary.