A complete solution to the partial scan problem.

To reduce the often unacceptable overhead penalty of scan design, a partial scan methodology is developed. In partial scan only a subset of flip-flops, necessary to test the given faults, is selected for scanning. The faults covered by scan tests are usually those not detected by functional vectors. Two methods for selecting scan flip-flops are described. In the first method, all possible tests are generated for each target fault. The tests are then processed to select one test for each fault such that a minimal set of flip-flops is used. The second method uses the distance heuristic of PODEM test generator. The flip-flop signals are made to appear at a large distance from primary inputs and outputs. The test generator thus avoids using flip-flop signals as much as possible. Examples of actual VLSI circuits show at least a 40-percent saving over the full-scan overhead. Additional advantages of partial scan are, 1) flip-flops that must violate scan design rules to meet functional requirements and those on critical path can be excluded from scan, and 2) Scan sequences are normally shorter.