A Digital Variable Time Interpolator Chip.

This memorandum presents a custom VLSI implementation of a digital variable time interpolator algorithm. The 7x7 mil(2) 2.5micron CMOS chip has the potential of reducing the overall costs by replacing a custom board in data modem applications. An interpolation scheme based on a polynomial approximation with finite impulse response filters (FIR) as the coefficients of polynomial is presented. Different architectures for VLSI implementation are compared. The architecture selected has a ROM based parametric transversal filter structure. The ROM is external and contains the filter coefficient sets for different parameter values. The custom chip implementation consists of a multiplier-accumulator, input registers for the data and the coefficients, microcoded ROM, address generator for the external ROM and the internal clock generator. At present, testing of the chip is in progress.