A Distributed Modeling Approach for Simulation and Verification of Digital Designs

A new modeling approach for simulation and verification of digital designs is presented in this paper and has been implemented for functional and fault simulation and timing verification in the experimental rule-based design verifier (RDV) [5] at Stanford University that uses Ada [2], [6] as the hardware description language and a simulation environment. In this approach, every component of a digital design is represented as a model-a concurrently executable entity that performs the tasks of scheduling itself for execution, simulation, or verification of the corresponding component, and communication of results to other devices.