A DSP with Caches - A Performance Study of the GSM-EFR Codec on the TI C6211

Texas Instruments has announced three new versions of its C62xx DSP architecture, the C6201B, C6202 and the C6211. The first two are incremental improvements over the C6201, namely improvements in clock frequency (both) and the amount of on-chip memory (C6202). The C6211, however, has a new on-chip memory architecture that uses a two-level cache hierarchy, something not typically seen on a DSP. This paper presents results of a performance study of the TI C6211 running the GSM-EFR speech codec. The overall performance is compared against the other C62xx devices, as well as to the Lucent DSP 16000 (Sabre). A detailed analysis of the cache performance shows that the caches, although small, are effective in maintaining good performance, even in a multi-programmed workload, where cache pollution affects the memory system performance. In addition, the performances of cache organizations other than the one implemented by the C6211 are analyzed.