A dynamic reconfiguration technique for the implementation of finite state machines.

This paper describes a novel technique for implementing finite state machines using dynamic reconfiguration. In the spirit of the term first introduced by Keller and Brebner et al., the technique may be described as a "hardware decelerator". The idea is to exploit spare block RAM resources to implement FSMs using fewer LUTs. The background rationale for such a technique is the availability of spare BRAMs 'for free' in Platform FPGAs. Detailed case studies of the concept are presented with a methodology producing LUT savings of up to 47%. The technique enables greater design mapping flexibility whilst still meeting requirements.