A Fault-Collapsing Analysis in Sequential Logic Networks

* M. A. Breuer is with the Departments of Electrical Engineering and Computer Science, University of Southern California, Los Angeles, California. 2259 just stated. A natural question is, What are the checkpoints in a sequential circuit? It is well known that by cutting all the feedback lines, a sequential network can be mapped into a combinational network. A reasonable approach would be to apply Bossen and Hong's labeling procedure to the resulting combinational network. The checkpoints obtained would then include all the feedback lines. In this paper, we show that in general all these feedback lines need not be checkpoints under a relation called "delay-equivalence" to be defined later. We will see that the number of checkpoints can be greatly reduced for a highly sequential logic network if our results are utilized. This, in turn, greatly reduces computational complexities for multiple fault analysis in sequential networks. A possible application of our results can be found in a paper by Chang, Su, and Breuer. 2