A FIFO ASIC (Application Specific IC) Chip for Use in a Ring Network

This talk will discuss the Dual FIFO chip developed as a part of the IRN project. It will present background information on the IMS racket switch and the rationale behind the development of a three-chip ring interface. The methodology used to design these chips will be presented with specific examples from the Dual FIFO. The talk will conclude with an examination of certain lessons learned by the author in undergoing the ASIC design process.