A Floating Point Radix 2 Shared Division/Square Root Chip

This paper presents the architecture and implementation of a full-custom 1.2 micron CMOS VLSI chip that executes a shared division/square root algorithm operating only on the mantissas (23-b in length) of single precision IEEE 754 1985 std. floating point numbers. The division and square root algorithms used in this implementation are the radix 2 signed digit based digit-by- digit schemes. These two algorithms perform quotient/root digit selection using two most-significant digits of the partial remainder. Previously proposed shared division square-root algorithms require more than two most-significant digits of the partial remainder to be observed during quotient or root operation. The proposed scheme is therefore faster than previous schemes. This implementation runs at a clock rate of about 66 MHz at 5.0V (from simulations) and requires 29 cycles per divide/square root operation from the time the operands are provided at its pin inputs.