A Hardware Implementation of LPC-10e

The viability of real-time narrow-band voice coding with good speech quality and high intelligibility will be demonstrated. We describe a hardware implementation of the U.S. Government Enhanced Linear Predictive Coder (LPC-10e) [1,2] operating at 2400 bits per second. This design is a prototype of the voice-processor hardware in the AT&T version of the new generation of secure telephones to be used in the U.S. Government Future Secure Voice System. The voice-processor prototype, operating in full-duplex mode with telephone handsets, will be available for demonstration. The implementation employs two Texas Instruments TMS320C25 digital signal processors operating at 8.0 MHz. One device handles both the analysis of the incoming speech signal and the interface to the channel. The encoded speech received from the channel is passed to the second device which does the voice synthesis. An AT&T T-7520 15-bit linear single-chip CODEC is used for PCM encoding and decoding. The entire system is mounted on a 400cm2 board and consumes 6 W. In the final version of the hardware, additional CMOS devices, surface mount technology, the use of PALs, and denser memories will reduce the area requirements, chip count, and power consumption.