A high efficient common IPC for LTE Layer1 multi-core DSP/SoC system
13 October 2014
This paper makes several contributions to the common IPC development. The first one is the shared memory self-healing circular buffer design. This shared memory based design supports zero-copy, so as to improve the IPC efficiency. This design also supports self-check and self-recovery, so as to achieve the self-healing reliability. The second one is the inter-core N senders - 1 receiver IPC channel design. The third one is the IPC commonizing and optimization for multi-core system. Our evaluation shows the advantages of this common IPC. 1) It is common and transparent to upper layers, so it supports the flexibly task-core mapping. 2) It is a high efficient IPC. After the optimization, in the 256 bytes message inter-core IPC case, it is 4.5 times faster than the same IPC in SmartOS.