A High Performance Reconfigurable Parallel Processing Architecture

The architecture of the AT&T DSP-3 parallel processor is described. The DSP-3 design is modular and, when implemented with 128 processing nodes, provides a maximum throughput of 3.2 GFLOPS (32 but floating point). The high speed interconnection network (40 Mbytes/sec contains redundant paths that allow the machine to be configured in a variety of topologies. This flexibility supports efficient operation for a diverse set of signal processing applications and enables topology reconfiguration in support of fault tolerance.