A High Speed 6x6 Bit Parallel Multiplier Using Self-Aligned Refractory Gate GaAs/AlGaAs Heterostructure FETs
A 6x6 bit parallel multiplier has been implemented in the 1- um Self-Aligned GaAs/AlGaAs Heterostructure FET (HFET) technology to demonstrate the design and fabrication capabilities of an LSI GaAs pilot production line. The chips are fully functional with a multiplication time of 5. 0 ns. This is equivalent to a delay of 156 ps/gate. Power dissipation is 440 mW (0.95 mW/gate).