A High-Speed Protocol Parallel Implementation: Design and Analysis

This paper presents a detailed multiprocessor architecture for the parallel implementation of the MultiSteam Protocol, MSP, a new feature-rich transport protocol. The parallelism of the protocol implementation is based on protocol functions such as error correction, error notification, etc. By dividing the processing based on protocol functionality, the architecture not only achieves high throughput, but reduces the end-to-end processing latency of the protocol as well. In addition, the variation, or jitter, in the interpacket arrival times at the protocol receiver is stabilized. Analysis of a software implementation of MSP using the architecture presented in this paper demonstrates that if 10-MIPS processors are used to implement the protocol, and practical hardware support is used, the architecture may support over 1 Gbps of throughput at the transport layer.