A Lithographic Mask System for MOS Fine-Line Process Development

In the past, the development of new silicon integrated circuit processes was impeded by the fact that an adequate set of simple test structures usually could not be fabricated without resorting to the full set of six lithographic levels required by the Poon Tester Chips.1 This set sometimes requires several months to fabricate if X-ray lithography 1107 is used. If device wafers could not be sacrificed, the processing engineer had to resort to simulating device structures, either by using metal dots of fixed areas on unpatterned oxides or deposited films, or by other schemes such as the use of offset circular windows using a pair of photolithographic steps.2,3 A set of photolithographic masks has been designed and is now available to fill the process development gap. The goal has been to provide the processing engineer with the means to simulate critical processing steps by introducing a monitor wafer, prepared in advance by one photolithographic step, and usually requiring only one more lithographic step of any type to obtain a structure ready for electrical testing. The full set of fine-line process development masks consists of six photolithographic levels, but these have been designed to be utilized in subsets of 2, 3, or 4 levels only. Available structures include metaloxide-semiconductor (MOS)* capacitors, contact windows, guarded and unguarded Schottky diodes, van der Pauw patterns, insulated gate field-effect transistors (IGFETs), gated diodes, and tapped electromigration test strings.