A Low Noise CMOS Fabricated 100K ECL Output Buffer (NOT PUBLISHED)

A CMOS output buffer which generates 100KECL logic levels is demonstrated. The final output stage consists of a single P-channel device. The voltage which is applied to the gate of this device is varied in a controlled manner to insure that the instantaneous current change (or de/dt) is significantly reduced. When 64 output buffers switch simultaneously at a clock rate of 175MHz, only 30mV of ground bounce is detected in a circuit simulation.