A low power, high speed ion implanted JFET for InP based monolithic optoelectronic ICs.

We describe a high performance, fully ion implanted InP Junction FET developed for the monolithic integration of optoelectronic circuits. This fully planar device is fabricated by a shallow (4000angstroms) n-channel implant, an n sup + source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000angstroms) abrupt pn junction, followed by a rapid thermal activation. From FETs with gates 2micron long, a transconductance of 50 mS/mm and an output impedance of 400 ohms-mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. These data translate into a cut off frequency of 6.6 GHz and an inverter gain of 20. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at V sub (gs) =0 V with negligible drift.