A Mechanism for Interconnecting High-Speed Hosts and LANS via an ATM Network, and Analysis of it's End-to-End Delays

This paper presents a mechanism for interconnecting high-speed Hosts and high-speed LANs via an ATM Network. Also presented are upper bound estimates of the end-to-end delays for varying conditions of network traffic. The mechanism proposes the use of a simple bandwidth arbitration scheme among network end-points to avoid focusing while interconnecting high-speed end-devices operating at rates ranging up to 100 Mbps. From the delay analysis, we see that the mechanism presented here is viable, especially when the end-devices are expected to exchange large data blocks.