A Method for Digitally Simulating Shorted Input Diode Failures

Digital fault simulation is the method of predicting the behavior under failure of a logical circuit by a computer program: that is, the use of a computer to aid in computing the output(s) of a logical circuit for a given input or a given set of inputs. 1 One of the drawbacks of existing digital fault simulators is that the class of failures capable of being simulated is somewhat restrictive. Most simulators, such as IBM's Saturn Fault Simulator and Seshu's Sequential Analyzer (see Refs. 2 and 3) consider only those failures which cause some connection in the logic circuit to appear stuck at "1" (stuck-at-1 )or stuck at "0" (stuck-at-0) .* Shorted input diode failures of low level logic (LLL) gates, for example, therefore cannot be simulated because they are not describable by stuck-at-1 or stuck-at-0 types of faults. In this paper we describe a method illustrating how shorted input diode failures can be simulated digitally, using a technique somewhat * Other common assumptions made are (i) the fault-free circuit is well b e h a v e d ; (ii) the class of faults considered is finite and n o n i n t e r m i t t e n t ; and (Hi) the single-fault assumption is used. 1957