A Model Compilation Approach for Optimized Implementations of Signal-Processing Systems onto Multi-Processor Systems-on-Chip

To meet the computational requirements of future 5G networks, the signal-processing functions of baseband stations and user equipments will be accelerated onto programmable, configurable and hard-wired components (e.g., CPUs, FPGAs, hardware accelerators). This urges the need to generate efficient implementations for such mixed architectures. Existing model-based approaches generate executable implementations of Systems-on-Chip (SoCs) by translating models into multiple SoC-programming languages (e.g., C/C++, OpenCL, Verilog/VHDL). However, these translations do not typically consider the optimization of non-functional properties (e.g., memory footprint, scheduling). This paper proposes a novel approach where system-level models are optimized and compiled into multiple implementations for different SoC architectures. We show the effectiveness of our approach with the compilation of UML/SysML models of a 5G decoder. Our solution generates, from a single Platform-Specific model, both a software implementation for a Digital Signal Processor platform and a hardware-software implementation for a platform based on hardware Intellectual Property (IP) blocks. Overall, we achieve a memory footprint reduction of 62% in the first case and 30% in the second case.